TI
SN74LVC1G08DCKR1.65V~5.5V 3.6ns@3.3V 10uA SC-70-5 Gates and Inverters RoHS
From
₹7.06
3,30,040 in stock
TOSHIBADatasheet (PDF)
TC7SET32FU,LJ(CT
OR Gate IC 1 Channel SSOP-5
SSOP-5ROHS3 CompliantActive
2-Input OR Gate
- Manufacturer
- TOSHIBA
- Manufacturer part #
- TC7SET32FU,LJ(CT
- Store part #
- C7360615
- Package / case
- SSOP-5
- Category
- Gates and Inverters
- Packaging
- Tape & Reel (TR)
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement · policy
2,670 in stock
#C7360615
Stock & price checked 26 h ago
| Quantity | Unit price | Pack price |
|---|---|---|
| 5+ | ₹13.55 | ₹67.75 |
| 50+ | ₹10.60 | ₹530.00 |
| 150+ | ₹9.13 | ₹1,369.50 |
| 500+ | ₹8.02 | ₹4,010.00 |
| 3,000+ | ₹7.14 | ₹21,420.00 |
| 6,000+ | ₹6.69 | ₹40,140.00 |
5 × ₹13.55
₹67.75
excl. GST
₹79.94 incl. 18% GST
- Dispatch in 7–10 working days
- GST invoice with every order
- Standard pack: 3,000 per reel
TC7SET32FU,LJ(CT
₹67.75 for 5 + GST
Specifications
- Input Type
- TTL-compatible CMOS
- Logic Family
- TC7SET Series
- Voltage - Supply
- 4.5V~5.5V
- Output Logic Level - Low
- 0V~100mV;360mV
- Propagation Delay
- 4.2ns@5V,15pF
- Features
- Overvoltage-tolerant input
- Input Logic Level - Low
- 800mV
- Operating Temperature
- -40℃~+85℃
- Input Logic Level - High
- 2V
- Output Logic Level - High
- 4.4V~4.5V;3.94V
- Quiescent Current(Iq)
- 2uA
- Current - Output High(IOH)
- 8mA
- Number of Channels
- 1;2
- Current - Output Low(IOL)
- 8mA
Packaging & compliance
- RoHS
- ROHS3 Compliant
- Lifecycle
- Active
- Moisture sensitivity
- MSL 1 (unlimited)
- ECCN
- EAR99
- Packaging
- Tape & Reel (TR)
- Standard pack
- 3,000 / Reel
- Sold per
- Piece
- Minimum order
- 5 (multiples of 5)
- Unit weight
- 0.03 g
Overview
Key features
- AEC-Q100 (Rev. H)
- Wide operating temperature range: Topr = -40 to 125℃
- High-speed operation: tpd = 4.2 ns (typ.) (VCC = 5.0 V, CL = 15 pF)
- Low power consumption: ICC = 2.0 μA (max.) (Ta = 25℃)
- TTL output compatible: VIL = 0.8 V (max.), VIH = 2.0 V (min.)
- 5.5 V tolerant inputs
- Balanced propagation delay: tp(LH) ≈ tp(HL)
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