Varnitronics
TLC555CDR TI
TI

TLC555CDR

SOIC-8 Programmable Timers and Oscillators RoHS

PopularSOIC-8ROHS3 CompliantActive

Single-chip timing circuit

Manufacturer
TI
Manufacturer part #
TLC555CDR
Store part #
C6986
Package / case
SOIC-8
Packaging
Tape & Reel (TR)
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

88,380 in stock

#C6986

Stock & price checked 30 h ago

QuantityUnit pricePack price
5+₹30.96₹154.80
50+₹24.18₹1,209.00
150+₹21.27₹3,190.50
500+₹17.65₹8,825.00
2,500+₹14.84₹37,100.00
5,000+₹13.88₹69,400.00

5 × ₹30.96

₹154.80

excl. GST

₹182.66 incl. 18% GST

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  • GST invoice with every order
  • Standard pack: 2,500 per reel

TLC555CDR

₹154.80 for 5 + GST

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Specifications

Supply Current
170uA
Operating Temperature
0℃~+70℃
Features
Reset function
Output Current
100mA
Timer Number
1
Voltage - Supply
2V~15V

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
Moisture sensitivity
MSL 1 (unlimited)
ECCN
EAR99
Packaging
Tape & Reel (TR)
Standard pack
2,500 / Reel
Sold per
Piece
Minimum order
5 (multiples of 5)
Unit weight
0.228 g

Overview

The TLC555 is a monolithic timing circuit fabricated using TI LinCMOS™ technology. This timer is fully compatible with CMOS, TTL, and MOS logic devices and operates at frequencies up to 2MHz. Due to its high input impedance, this device supports smaller timing capacitors than those used with the NE555 or LM555. As a result, more accurate time delays and oscillations can be achieved. Low power consumption is maintained across the entire supply voltage range. Like the NE555, the TLC555 has a trigger level of approximately one-third of the supply voltage and a threshold level of approximately two-thirds of the supply voltage. These levels can be modified using the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output goes low. The reset input (RESET) takes priority over all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output goes low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and ground (GND). All unused inputs must be tied to an appropriate logic level to prevent false triggering.

Applications

  • Precision timing
  • Pulse generation
  • Sequential timing
  • Time delay generation
  • PWM
  • Pulse position modulation
  • Linear ramp generation

Key features

  • Ultra-low power consumption: 1mW (typical) at VDD = 5V
  • Operates in astable mode
  • CMOS output with rail-to-rail swing
  • High output current capability
  • Sink current: 100mA (typical)
  • Source current: 10mA (typical)
  • Output fully compatible with CMOS, TTL, and MOS
  • Low supply current with reduced spikes during output transitions
  • 2V to 15V single-supply operation
  • Functionally interchangeable with NE555; identical pinout
  • ESD protection exceeds 2000V per MIL-STD-883C Method 3015.2
  • Available in Q-grade temperature for automotive
  • High-reliability automotive applications
  • Configuration control and documentation support
  • Qualified to automotive standards

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