UCC27524ADR

The UCC27524A device is a dual-channel, highspeed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524A adds the ability to handle –5 V directly at the input pins for increased robustness. The UCC27524A is a dual non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A is capable of delivering high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay typically 13 ns. In addition, the drivers feature matched internal propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity. For safety purpose, internal pull-up and pull-down resistors on the input pins of the UCC27524A ensure that outputs are held LOW when input pins are in floating condition. UCC27524A features Enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation. UCC27524A family of devices are available in SOIC-8 (D), VSSOP-8 with exposed pad (DGN) packages.

Applications

• Switch-Mode Power Supplies
• DC-to-DC Converters
• Motor Control
• Solar Power
• Gate Drive for Emerging Wide Band-Gap Power Devices Such as GaN

Key features

• Industry-Standard Pin Out
• Two Independent Gate-Drive Channels
• 5-A Peak Source and Sink-Drive Current
• Independent-Enable Function for Each Output
• TTL and CMOS Compatible Logic Threshold Independent of Supply Voltage
• Hysteretic-Logic Thresholds for High Noise Immunity
• Ability to Handle Negative Voltages (–5 V) at Inputs
• Inputs and Enable Pin-Voltage Levels Not Restricted by VDD Pin
• Bias Supply Voltage 4.5 to 18-V Single-Supply Range
• Outputs Held Low During VDD-UVLO (Ensures Glitch-Free Operation at Power Up and Power Down)
• Fast Propagation Delays (13-ns Typical)
• Fast Rise and Fall Times (7-ns and 6-ns Typical)
• 1-ns Typical Delay Matching Between 2-Channels
• Two Outputs are Paralleled for Higher Drive Current
• Outputs Held in Low When Inputs Floating
• SOIC-8, HVSSOP-8 PowerPAD Package Options
• Operating Temperature Range of –40 to 140°C