74AUP1G57GW,125

The 74AUP1G57 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Applications

• Low-power applications
• High noise immunity applications
• Overvoltage protection applications
• Low quiescent current applications
• Partial power-down mode applications

Key features

• Wide supply voltage range from 0.8 V to 3.6 V
• CMOS low power dissipation
• High noise immunity
• Overvoltage tolerant inputs to 3.6 V
• Low noise overshoot and undershoot <10 % of VCC
• IOFF circuitry provides partial power-down mode operation
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Low static power consumption; ICC = 0.9 μA (maximum)
• Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V), JESD8-11 (0.9 V to 1.65 V), JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃