74AUP1T34GW,125

The 74AUP1T34 is a single dual supply translating buffer. Input A is referenced to VCC(A) and output Y is referenced to VCC(Y). Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 1.1 V to 3.6 V. This device is fully specified for partial power down applications using lOFF. The lOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Key features

• Wide supply voltage range from 1.1 V to 3.6 V
• CMOS low power dissipation
• High noise immunity
• Complies with JEDEC standards: JESD8 - 7 (1.2 V to 1.95 V), JESD8 - 5 (1.8 V to 2.7 V), JESD8 - B (2.7 V to 3.6 V)
• Wide supply voltage range: VCC(A): 1.1 V to 3.6 V, VCC(Y): 1.1 V to 3.6 V
• Low static power consumption; ICC = 0.9 μA (maximum)
• Each port operates over the full 1.1 V to 3.6 V power supply range
• Latch - up performance exceeds 100 mA per JESD 78 Class II Level B
• Overvoltage tolerant inputs to 3.6 V
• Low noise overshoot and undershoot < 10 % of VCC
• IOFF circuitry provides partial Power - down mode operation
• ESD protection: HBM: ANSI/ESDA/JEDEC JS - 001 class 3A exceeds 5000 V, CDM: ANSI/ESDA/JEDEC JS - 002 class C3 exceeds 1000 V
• Multiple package options
• Specified from - 40 ℃ to + 85 ℃ and - 40 ℃ to + 125 ℃