74HC390D,653-JSM

The 74HC/HCT390 is a dual 4-bit decade asynchronous counter comprising four independently clocked divide units: two divide-by-2 units and two divide-by-5 units. All units share a common asynchronous master reset input, supporting BCD decade or bi-quinary configurations. When master reset inputs 1MR and 2MR are used simultaneously to clear all 8-bit counters, multiple counting configurations can be realized within a single package. The divide unit clocks nCP0 and nCP1 support asynchronous counter or frequency division applications with division factors of 2, 4, 5, 10, 20, 25, 50, or 100. Each divide unit is triggered on the high-to-low transition of the clock input. For BCD decade operation, connect the nQ0 output to the clock input of the divide-by-5 unit; for bi-quinary operation, connect the nQ3 output to the clock input of the divide-by-5 unit, with nQ0 serving as the decade output. When the nMR input is HIGH, it overrides the clock and forces all outputs LOW. Input clamping diodes are provided, allowing signals exceeding VCC to be connected via current-limiting resistors.

Key features

• Input levels: 74HC390 — CMOS, 74HCT390 — TTL
• Dual BCD decade or divide-by-2/5 counters
• Single device configurable for divide-by-2, 4, 5, 10, 20, 25, 50, or 100
• Dual master reset inputs for independent clearing of each decade counter
• Operating temperature range: -40℃ ~ +125℃
• Package options: DIP16 / SOP16 / TSSOP16