Varnitronics
74HC40103D,653 Nexperia
Nexperia

74HC40103D,653

Rising Edge 1 32MHz SOIC-16 Counters, Dividers RoHS

SOIC-16ROHS3 CompliantActive

8-bit synchronous binary down counter

Manufacturer
Nexperia
Manufacturer part #
74HC40103D,653
Store part #
C148205
Package / case
SOIC-16
Packaging
Tape & Reel (TR)
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

4,572 in stock

#C148205

Stock & price checked 40 h ago

QuantityUnit pricePack price
1+₹85.28₹85.28
10+₹68.31₹683.10
30+₹60.04₹1,801.20
100+₹51.56₹5,156.00
500+₹46.56₹23,280.00
1,000+₹43.95₹43,950.00

1 × ₹85.28

₹85.28

excl. GST

₹100.63 incl. 18% GST

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  • GST invoice with every order
  • Standard pack: 2,500 per reel

74HC40103D,653

₹85.28 for 1 + GST

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Specifications

Logic Family
74HC
Voltage - Supply
2V~6V
Direction
Down Counter
Trigger Type
Rising Edge
Timing
Synchronous
Operating Temperature
-40℃~+125℃
Reset
Asynchronous
Number of Elements
1
Propagation Delay
35ns
Count Rate
32MHz
Features
Synchronous counting;Asynchronous parallel load;Cascade counter;Reset function

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
Moisture sensitivity
MSL 1 (unlimited)
ECCN
EAR99
Packaging
Tape & Reel (TR)
Standard pack
2,500 / Reel
Sold per
Piece
Minimum order
1
Unit weight
0.275 g

Overview

The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition regardless of the state of TE. When the asynchronous preset enable input (PL(overline)) is LOW, data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE, TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word. When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal 255) regardless of the state of any other input. If all control inputs except TE are HIGH at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 256 clock pulses long. Device may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Applications

  • Divide-by-n counters
  • Programmable timers
  • Interrupt timers
  • Cycle/program counters

Key features

  • Cascadable
  • Synchronous or asynchronous preset
  • Wide supply voltage range from 2.0 V to 6.0 V
  • CMOS low-power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standard no. 7A
  • CMOS input levels
  • ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +80 °C and from -40 °C to +125 °C

Alternatives

Similar parts — check the datasheet before substituting.

CD74HC40103M96#C2675499TI · SOIC-16₹82.56 · 52 in stockView
CD40103BDR(LX)#C22390229lingxingic · SOP-16₹70.86 · 338 in stockView
CD74HC40103QM96EP#C2878020TI · SOIC-16₹711.13 · 10 in stockView
CD40103BNSR#C2870833TI · SO-16₹289.86 · 10 in stockView
V62/04702-01XE#C3828717TI · SOIC-16₹291.67 · 0 in stockView

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