74HC40103D,653-JSM

74HC40103D,653 - JSM is an 8-bit synchronous down counter. It features control inputs for enabling or disabling the clock (CP), clearing the counter to its maximum count value, and synchronously or asynchronously presetting the counter. In normal operation, the counter decrements by one count on each rising edge of the clock (CP). Counting is inhibited when the Terminal Enable input (TE) is HIGH. If TE is LOW, the Terminal Count output (TC) goes LOW when the count reaches zero and remains LOW for one complete clock cycle. When the Synchronous Preset Enable input (PE) is LOW, data on the Jam inputs (P0 to P7) is clocked into the counter on the next rising clock edge, regardless of the state of TE. When the Asynchronous Preset Enable input (PL) is LOW, data on the Jam inputs (P0 to P7) is asynchronously forced into the counter, regardless of the states of PE, TE, or CP. The Jam inputs (P0 to P7) represent an 8-bit binary word. When the Master Reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count value (decimal 255), regardless of the states of all other inputs. If all control inputs except TE are HIGH when the count is zero, the counter jumps to the maximum count value, forming a counting sequence 256 clock pulses long. The device can be cascaded in synchronous or ripple mode using the TE input and TC output. Inputs include clamping diodes, enabling input interfacing to voltages exceeding VCC using current-limiting resistors. Package: SOP-16.

Key features

• Cascadable
• Synchronous or asynchronous preset
• Low power consumption
• CMOS input levels
• Operating temperature range: -40℃ to +125℃
• Package: SOP16