74HC4050D,653-JSM

74HC4050D,653 - JSM is a 5-stage Johnson decade counter featuring ten spike-free decoded active-HIGH outputs (Q0 to Q9), an active-LOW carry output from the most significant flip-flop (Q5–9), active-HIGH and active-LOW clock inputs (CP0, CP1), and a priority asynchronous master reset input (MR). The counter advances on a LOW-to-HIGH transition of CP0 when CP1 is LOW, or on a HIGH-to-LOW transition of CP1 when CP0 is HIGH. When cascading counters, the Q5–9 output is LOW during states 5, 6, 7, 8, and 9, and can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5–9 = HIGH; Q1 to Q9 = LOW), regardless of the clock inputs (CP0, CP1). The internal circuitry provides automatic counter code correction: following any illegal code, the counter returns to normal counting mode within 11 clock pulses. The recommended supply voltage range for this counter is 3V to 15V with respect to VSS (typically ground). Unused inputs must be connected to VDD, VSS, or other inputs.

Key features

• Wide supply voltage range: 3V to 15V
• Automatic counter correction
• Tolerates slow clock rise and fall times
• Parametric ratings at 5V, 10V, and 15V
• Standardized symmetrical output characteristics
• Operating temperature range: -40℃ to +125℃
• Package: SOP16