74LVC1G97GV

The 74LVC1G97 is a configurable multi-function gate with Schmitt-trigger inputs. This device can be configured via 3-bit inputs to implement any of the following logic functions: multiplexer, AND, OR, NAND, NOR, inverter, or buffer. All inputs can be connected directly to VCC or GND. Inputs can be driven by 3.3V or 5V devices, allowing these devices to be used as level translators in mixed 3.3V/5V environments. This device is fully specified for partial power-down applications using IOFF. The IOFF circuit disables the outputs, preventing potentially damaging backflow currents when the device is powered down.

Key features

• Wide supply voltage range: 1.65V to 5.5V
• Overvoltage-tolerant inputs up to 5.5V
• High noise immunity
• ±24 mA output drive capability (at VCC = 3.0 V)
• CMOS low power consumption
• Latch-up performance exceeds 200 mA
• Direct TTL-level interface compatible
• IOFF circuit enables partial power-down mode operation
• JEDEC standards compliant: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
• Multiple package options