CD4017SA16.TR

CD4017 is a 5-stage Johnson decade counter with ten spike-free decoded active-HIGH outputs (Q0 to Q9), an active-LOW carry output (Q5-9) from the most significant flip-flop, active-HIGH and active-LOW clock inputs (CP0, CP1), and an overriding asynchronous master reset input (MR). The counter advances on the LOW-to-HIGH transition of CP0 when CP1 is LOW, or on the HIGH-to-LOW transition of CP1 when CP0 is HIGH. For cascading counters, the Q5-9 output, which is LOW when the counter is in states 5, 6, 7, 8, and 9, can be used to drive the CP0 input of the next stage. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW), independent of the clock inputs (CP0, CP1). Internal circuitry provides automatic counter code correction: following any illegal code, the counter returns to the correct counting sequence within 11 clock pulses. The recommended operating supply voltage VDD ranges from 3V to 15V (with respect to VSS, typically ground). Unused inputs must be connected to VDD, VSS, or another input.

Key features

• Wide supply voltage range: 3V to 15V
• Automatic counter correction
• Tolerates slow clock rise and fall times
• Available with 5V, 10V, and 15V parametric ratings
• Standardized symmetrical output characteristics
• Operating temperature range: -40℃ to +125℃
• Package options: DIP16/SOP16/TSSOP16