CD4518BDRG

The CD4518B dual BCD up-counter and CD4520B dual binary up-counter each consist of two identical internally synchronous 4-stage counters. The counter stages are D-type flip-flops with interchangeable clock and enable lines, allowing incrementing on either the rising or falling edge. For single-unit operation, the enable input is held high and the counter increments on each rising edge of the clock. The counters can be cleared by a high level on their reset lines. Counters can be cascaded in ripple mode by connecting Q4 to the enable input of the subsequent counter while holding the latter's clock input low.

Applications

• Multi-stage synchronous counting
• Multi-stage ripple counting
• Frequency divider

Key features

• High-voltage type (20V rated)
• CD4518B dual BCD up-counter
• CD4520B dual binary up-counter
• Medium-speed operation: typical clock frequency of 6MHz at 10V
• Positive- or negative-edge triggered
• Synchronous internal carry propagation
• 100% static current testing at 20V
• 5V, 10V, and 15V parametric ratings
• Maximum input current of 1µA at 18V over full package temperature range; 100nA at 18V and +25°C
• Noise immunity (over full package/temperature range)
• 1V at VDD = 5V
• 2V at VDD = 10V
• 2.5V at VDD = 15V
• Standardized symmetrical output characteristics
• Meets all requirements of JEDEC Tentative Standard No. 13B "Standard Specifications for Description of 'B' Series CMOS Devices"
• DIP-16 package
• SOP-16 package
• TSSOP-16 package