Varnitronics
CD74HC4017E TI
TI

CD74HC4017E

Rising Edge 1 35MHz DIP-16 Counters, Dividers RoHS

DIP-16ROHS3 CompliantActive

High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

Manufacturer
TI
Manufacturer part #
CD74HC4017E
Store part #
C354048
Package / case
DIP-16
Packaging
Tube-packed
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

1,671 in stock

#C354048

Stock & price checked 6 days ago

QuantityUnit pricePack price
1+₹118.38₹118.38
10+₹102.35₹1,023.50
25+₹91.06₹2,276.50
100+₹81.75₹8,175.00
500+₹78.93₹39,465.00
1,000+₹77.20₹77,200.00

1 × ₹118.38

₹118.38

excl. GST

₹139.69 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 7–10 working days
  • GST invoice with every order
  • Standard pack: 25 per tube

CD74HC4017E

₹118.38 for 1 + GST

Specifications

Logic Family
74HC
Voltage - Supply
2V~6V
Direction
Up Counter
Trigger Type
Rising Edge
Timing
Synchronous
Operating Temperature
-55℃~+125℃
Reset
Asynchronous
Number of Elements
1
Propagation Delay
19ns
Count Rate
35MHz
Features
Static operation;Reset function;Cascade counter

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
ECCN
EAR99
Packaging
Tube-packed
Standard pack
25 / Tube
Sold per
Piece
Minimum order
1
Unit weight
1.875 g

Overview

The ’HC4017 is a high speed silicon gate CMOS 5 - stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock period cycle. The CARRY (TC) output transitions low to high after OUTPUT 10 goes from high to low, and can be used in conjunction with the CLOCK ENABLE (CE) to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET (MR) input is also provided which when taken high sets all the decoded outputs, except *0*, low. The device can drive up to 10 low power Schottky equivalent loads.

Key features

  • Fully Static Operation
  • Buffered Inputs
  • Common Reset
  • Positive Edge Clocking
  • Typical fMAX = 50MHz at Vcc = 5V, CL = 15pF, TA = 25℃
  • Fanout (Over Temperature Range) - Standard Outputs: 10 LSTTL Loads - Bus Driver Outputs: 15 LSTTL Loads
  • Wide Operating Temperature Range: -55℃ to 125℃
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, N1μ = 30% of Vcc at Vcc = 5V

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