EnergyMath

EM74LVC2G34GM

Schmitt trigger 1.65V~5.5V 1 2 2.5ns@3.3V,50pF DFN-6(1x1.5) Buffers, Drivers, Receivers, Transceivers

DFN-6(1x1.5)RoHSActive

Dual buffer gate

Manufacturer: EnergyMath
Manufacturer part #: EM74LVC2G34GM
Store part #: C49188092
Package / case: DFN-6(1x1.5)
Category: Buffers, Drivers, Receivers, Transceivers
Packaging: Tape & Reel (TR)

Datasheet (PDF)

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2,920 in stock

#C49188092

Stock & price checked 5 days ago

Quantity	Unit price	Pack price
5+	₹15.23	₹76.15
50+	₹12.04	₹602.00
150+	₹10.44	₹1,566.00
500+	₹9.25	₹4,625.00
3,000+	₹8.30	₹24,900.00
6,000+	₹7.82	₹46,920.00

Quantity (min 5, multiples of 5)

5 × ₹15.23

₹76.15

excl. GST

₹89.86 incl. 18% GST

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Standard pack: 3,000 per reel

EM74LVC2G34GM

₹76.15 for 5 + GST

Specifications

Input type: Schmitt trigger
Voltage - Supply: 1.65V~5.5V
Operating Temperature: -40℃~+125℃
Quiescent Supply Current: 4uA
Function: Level shifting;Power-off isolation
Current - Output High(IOH): 24mA
Series: 74LVC
Current - Output Low(IOL): 24mA
Number of Bits per Element: 1
Channel Type: Unidirectional
Number of Elements: 2
Propagation Delay: 2.5ns@3.3V,50pF

Packaging & compliance

RoHS: RoHS
Lifecycle: Active
Packaging: Tape & Reel (TR)
Standard pack: 3,000 / Reel
Sold per: Piece
Minimum order: 5 (multiples of 5)
Unit weight: 0.027 g

Overview

The EM74LVC2G34 is a dual buffer. Its inputs can be driven by 3.3V or 5V devices. This feature allows the device to be used as a level translator in mixed 3.3V and 5V environments. Schmitt-trigger action on all inputs makes the circuit tolerant of slower input rise and fall times. The device is fully suitable for partial power-down applications using the I_OFF circuit. The I_OFF circuit disables the outputs, preventing damaging backflow current when the device is powered down.

Key features

Wide supply voltage range: 1.65V to 5.5V
Input overvoltage tolerance up to 5.5V
High noise immunity
±24 mA output drive capability (at VCC = 3.0 V)
CMOS low power consumption
Direct TTL-level interface compatible
I_OFF circuit for partial power-down mode operation
Latch-up performance exceeds 100 mA
Compliant with JEDEC standards: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD36 (4.6 V to 5.5 V)
Dual-buffered gate