MXIC
MX25L25645GM2I-08G
FLASH - NOR Memory IC 256Mbit SPI 133MHz SOP-8-208mil
SOP-8-208milRoHSActive
CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY
Datasheet (PDF)
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement · policy
52,457 in stock
#C190799
Stock & price checked 6 days ago
| Quantity | Unit price | Pack price |
|---|---|---|
| 1+ | ₹644.29 | ₹644.29 |
| 10+ | ₹553.24 | ₹5,532.40 |
| 30+ | ₹499.14 | ₹14,974.20 |
| 100+ | ₹410.47 | ₹41,047.00 |
| 500+ | ₹385.27 | ₹1,92,635.00 |
| 1,000+ | ₹373.76 | ₹3,73,760.00 |
1 × ₹644.29
₹644.29
excl. GST
₹760.26 incl. 18% GST
- Dispatch in 7–10 working days
- GST invoice with every order
- Standard pack: 2,000 per reel
MX25L25645GM2I-08G
₹644.29 for 1 + GST
Specifications
- Operating Temperature
- -40℃~+85℃
- Features
- Write enable latch;Hardware write protection;Software write protection;Absolute write protection
- Memory Size
- 256Mbit
- Voltage - Supply
- 2.7V~3.6V
- Program / Erase Cycles
- 100,000 cycles
- Clock Frequency
- 120MHz
- Data Retention - TDR (Year)
- 20 Years
- Page Programming Time (Tpp)
- 750us
- Interface
- SPI
Packaging & compliance
- RoHS
- RoHS
- Lifecycle
- Active
- ECCN
- 3A991b1a
- Packaging
- Tape & Reel (TR)
- Standard pack
- 2,000 / Reel
- Sold per
- Piece
- Minimum order
- 1
- Unit weight
- 0.239 g
Overview
Key features
- Protocol Support - Single I/O, Dual I/O and Quad I/O
- Support DTR (Double Transfer Rate) Mode
- Support clock frequency up to 133MHz
- Supports Serial Peripheral Interface -- Mode 0 and Mode 3
- Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations
- 268,435,456×1 bit structure or 134,217,728×2 bits (two I/O mode) structure or 67,108,864×4 bits (four I/O mode) structure
- Latch-up protected to 100mA from -1V to Vcc + 1V
- Low Vcc write inhibit is from 1.5V to 2.5V
- Fast read for SPI mode - Support clock frequency up to 133MHz for all protocols - Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions
- Configurable dummy cycle number for fast read operation
- Quad Peripheral Interface (QPI) available
- Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually
- Programming: - 256byte page buffer - Quad Input/Output page program(4PP) to enhance program performance
- Typical 100,000 erase/program cycles
- 20 years data retention
- Input Data Format - 1-byte Command code
- Advanced Security Features - Block lock protection
Alternatives
Similar parts — check the datasheet before substituting.
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