SN74AUP2G125YZPR

The AUP family ensures a very low static and dynamic power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity. The SN74AUP2G125 is a dual bus buffer gate designed for 0.8-V to 3.6-V V_CC operation. This device features dual line drivers with 3-state outputs. Each output is disabled when the corresponding output-enable (OE(overline)) input is high. This device has the input-disable feature, which allows floating input signals. This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Applications

• Point-to-point applications
• Battery-powered portable devices with low-power requirements

Key features

• Available in the Texas Instruments NanoStar Package
• Low Static-Power Consumption (I_CC = 0.9 μA Max)
• Low Dynamic-Power Consumption (C_pd = 4 pF Typ at 3.3 V)
• Low Input Capacitance (C_I = 1.5 pF Typ)
• Low Noise – Overshoot and Undershoot < 10% of V_CC
• Input-Disable Feature Allows Floating Input Conditions
• I_off Supports Partial-Power-Down Mode Operation
• Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• t_pd = 5.4 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Performance Tested Per JESD 22: 2000-V Human-Body Model (A114-B, Class II), 1000-V Charged-Device Model (C101)