Varnitronics
SN74HC191DR(LX) lingxingic
lingxingic

SN74HC191DR(LX)

Rising Edge 1 36MHz SOP-16 Counters, Dividers

SOP-16RoHSActive

Presettable Synchronous 4-bit Binary up/down Counter

Manufacturer
lingxingic
Manufacturer part #
SN74HC191DR(LX)
Store part #
C41413606
Package / case
SOP-16
Packaging
Tape & Reel (TR)
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

1,720 in stock

#C41413606

Stock & price checked 6 days ago

QuantityUnit pricePack price
5+₹28.33₹141.65
50+₹25.27₹1,263.50
150+₹23.96₹3,594.00
500+₹22.33₹11,165.00
2,500+₹19.81₹49,525.00
5,000+₹19.37₹96,850.00

5 × ₹28.33

₹141.65

excl. GST

₹167.15 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 7–10 working days
  • GST invoice with every order
  • Standard pack: 2,500 per reel

SN74HC191DR(LX)

₹141.65 for 5 + GST

Specifications

Logic Family
74HC
Voltage - Supply
2V~6V
Direction
Down Counter;Up Counter
Trigger Type
Rising Edge
Timing
Synchronous
Operating Temperature
-40℃~+125℃
Reset
Asynchronous
Number of Elements
1
Propagation Delay
21ns
Count Rate
36MHz
Features
Synchronous counting;Asynchronous parallel load;Multi-mode counting

Packaging & compliance

RoHS
RoHS
Lifecycle
Active
Packaging
Tape & Reel (TR)
Standard pack
2,500 / Reel
Sold per
Piece
Minimum order
5 (multiples of 5)
Unit weight
0.218 g

Overview

The SN74HC/HCT191 is an asynchronously presettable 4-bit binary up/down counter. It contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capability permits the counter to be preset to any desired value. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs when the parallel load (PL) input is LOW. This operation overrides the counting function. Counting is inhibited by a HIGH level on the count enable (CE) input. When CE is LOW internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The up/down (U /D) input signal determines the direction of counting as indicated in the function table. The CE input may go LOW when the clock is in either state, however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH. Also, the U/D input should be changed only when either CE or CP is HIGH. Overflow/underflow indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC). The TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches '15' in the count-up-mode. The TC output will remain HIGH until a state change occurs, either by counting or presetting, or until U/D is changed. Do not use the TC output as a clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the RC output. When TC is HIGH and CE is LOW, the RC output follows the clock pulse (CP). This feature simplifies the design of multistage counters. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Key features

  • Input levels: For SN74HC191: CMOS level For SN74HCT191: TTL level
  • Synchronous reversible counting
  • Asynchronous parallel load
  • Count enable control for synchronous expansion
  • Single up/down control input
  • Specified from -40 °C to +125 °C
  • Packaging information: DIP16/SOP16/TSSOP16

Alternatives

Similar parts — check the datasheet before substituting.

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