Varnitronics
SN74LS540DBR TI
TI

SN74LS540DBR

4.75V~5.25V 8 15ns@5V,45pF SSOP-20 Buffers, Drivers, Receivers, Transceivers RoHS

SSOP-20ROHS3 CompliantActive

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

Manufacturer
TI
Manufacturer part #
SN74LS540DBR
Store part #
C2877474
Package / case
SSOP-20
Packaging
Tape & Reel (TR)
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

139 in stock

#C2877474

Stock & price checked 4 days ago

QuantityUnit pricePack price
1+₹265.46₹265.46
10+₹222.85₹2,228.50
30+₹196.33₹5,889.90
100+₹168.93₹16,893.00
500+₹156.76₹78,380.00
1,000+₹151.32₹1,51,320.00

1 × ₹265.46

₹265.46

excl. GST

₹313.24 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 15-18 working days
  • GST invoice with every order
  • Standard pack: 2,000 per reel

SN74LS540DBR

₹265.46 for 1 + GST

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Specifications

Current - Output High(IOH)
15mA
Series
74LS
Voltage - Supply
4.75V~5.25V
Output Logic Level - Low
500mV
Input Logic Level - High
2V
Current - Output Low(IOL)
24mA
Input Logic Level -Low
600mV
Operating Temperature
0℃~+70℃
Number of Gates
8
Quiescent Supply Current
52mA
Propagation Delay
15ns@5V,45pF
Output Logic Level - High
2.4V~3.4V

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
ECCN
EAR99
Packaging
Tape & Reel (TR)
Standard pack
2,000 / Reel
Sold per
Piece
Minimum order
1
Unit weight
0.248 g

Overview

These octal buffers and line drivers are designed to offer the performance of the popular SN54LS240/SN74LS240 series, while featuring a pinout arrangement with inputs and outputs on opposite sides of the package. This layout significantly optimizes PCB routing. The three-state control gate is a 2-input NOR gate; when either G1 or G2 is high, all 8 outputs are placed in a high-impedance state. The LS540 provides inverted data at the outputs, while the LS541 provides non-inverted data. The SN74LS540 and SN74LS541 operate over a temperature range of 0℃ to 70℃.

Key features

  • Three-state outputs for driving buses or buffered memory address registers
  • PNP inputs reduce DC loading
  • Input hysteresis for improved noise margin
  • Flow-through pinout (all inputs and outputs on opposite sides of package)

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