SN74LVC2G132DCTR

Schmitt trigger 1.65V~5.5V 5ns@5V,50pF 10uA SSOP-8 Gates and Inverters RoHS

SSOP-8ROHS3 CompliantActive

Dual 2-Input NAND Gate With Schmitt-Trigger Inputs

Manufacturer: TI
Manufacturer part #: SN74LVC2G132DCTR
Store part #: C2870897
Package / case: SSOP-8
Category: Gates and Inverters
Packaging: Tape & Reel (TR)

Datasheet (PDF)

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5,039 in stock

#C2870897

Stock & price checked 6 days ago

Quantity	Unit price	Pack price
1+	₹82.75	₹82.75
10+	₹70.16	₹701.60
30+	₹61.04	₹1,831.20
100+	₹53.65	₹5,365.00
500+	₹51.27	₹25,635.00
1,000+	₹49.96	₹49,960.00

Quantity (min 1)

1 × ₹82.75

₹82.75

excl. GST

₹97.65 incl. 18% GST

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Standard pack: 3,000 per reel

SN74LVC2G132DCTR

₹82.75 for 1 + GST

Specifications

Input Type: Schmitt trigger
Logic Family: 74LVC Series
Voltage - Supply: 1.65V~5.5V
Output Logic Level - Low: 550mV~650mV
Propagation Delay: 5ns@5V,50pF
Features: Live insertion protection;Local shutdown mode;Rear drive protection
Input Logic Level - High: 1.16V~3.33V
Operating Temperature: -40℃~+125℃
Input Logic Level - Low: 390mV~1.87V
Output Logic Level - High: 3.8V
Quiescent Current(Iq): 10uA
Number of Channels: 2;2
Current - Output High(IOH): 32mA
Current - Output Low(IOL): 32mA

Packaging & compliance

RoHS: ROHS3 Compliant
Lifecycle: Active
ECCN: EAR99
Packaging: Tape & Reel (TR)
Standard pack: 3,000 / Reel
Sold per: Piece
Minimum order: 1
Unit weight: 0.08 g

Overview

This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V Vcc operation. The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A·B or Y = A + B in positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Key features

Available in Texas Instruments NanoFree™ Package
Supports 5-V Vcc Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5.3 ns at 3.3 V
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot) > 2V at VCC = 3.3V, TA = 25°C
Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection
Support Translation Down (5V to 3.3V and 3.3V to 1.8V)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)