SN74LVC2G86DCTR

This dual 2- input exclusive- OR gate is designed for 1.65- V to 5.5- V VCC operation. The SN74LVC2G86 performs the Boolean function Y = A⊕B or Y = AB + AB in positive logic. NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package. A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device is fully specified for partial- power- down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Applications

• True/complement element: when one input is LOW, the other input signal passes through non-inverted; when one input is HIGH, the other input signal is inverted
• Logic identity element: output asserted LOW when all inputs are at the same logic level
• Even parity element: output asserted LOW when an even number of inputs are active
• Odd parity element: output asserted HIGH when an odd number of inputs are active

Key features

• Available in the Texas Instruments NanoFreeTM Package
• Supports 5- V Vcc Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 4.7 ns at 3.3V
• Low Power Consumption, 10- A Max Icc
• ±24 - mA Output Drive at 3.3V
• Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25℃
• Typical VOHV (Output VOH Undershoot) >2V at VCC = 3.3V, TA = 25℃
• Ioff Supports Live Insertion, Partial- PowerDown Mode and Back Drive Protection
• Latch- Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22:
• 2000- V Human- Body Model (A114- A)
• 200- V Machine Model (A115- A)
• 1000- V Charged- Device Model (C101)