W958D8NBYA5I

HyperBus is a low pin count DDR interface that enables high-speed read and write throughput. The DDR protocol transfers two data bytes per clock cycle on the DQ I/O signals. Read and write transactions on HyperBus consist of a series of 16-bit wide, one-clock-cycle data transfers on the internal HyperRAM array, along with two corresponding 8-bit wide, half-clock-cycle data transfers on the DQ signals. All inputs and outputs are LV-CMOS compatible. Command, address, and data information are transferred through eight HyperBus DQ[7:0] signals. The clock (CK#, CK) is used by HyperBus slave devices to capture information when receiving commands, addresses, or data on the DQ signals. Command or address values are center-aligned with clock transitions. Each transaction begins with the assertion of CS# and the command-address (CA) signals, followed by clock transitions to transfer six CA bytes, then an initial access latency and read/write data transfer, until CS# is deasserted. Read and write transactions require two clock cycles to define the target row address and burst type, followed by an initial access latency of tACC. During the CA portion of the transaction, the memory indicates whether an additional delay for the required refresh time (tRFH) has been added to the initial latency by driving the RWDS signal high. During CA, the third clock cycle specifies the target word address within the target row. In read and write transactions, after the initial data value is output (or input), additional data can be read from (or written to) the row in subsequent clock cycles in either wrap or linear order. When configured for linear burst mode, the device automatically fetches the next consecutive row from the memory array to support continuous linear bursts. Accessing the next row in the array concurrently with ongoing read/write data transfers enables linear sequential burst operation, delivering a sustained data rate of 500 MB/s (1 byte (8-bit data bus) × 2 (data clock edges) × 250 MHz = 500 MB/s).

Key features

• Interface: HyperBus
• Power supply: 1.7V~2.0V
• Maximum clock rate: 250MHz
• Double-Data Rate (DDR) Up to 500 MB/s
• Clock:
• Single ended clock (CK)
• Differential clock (CK/CK#)
• Chip Select (CS#)
• 8-bit data bus (DQ[7:0])
• Hardware reset (RESET#)
• Read-Write Data Strobe (RWDS)
• Bidirectional Data Strobe / Mask
• Output at the start of all transactions to indicate refresh latency
• Output during read transactions as Read Data Strobe
• Input during write transactions as Write Data Mask
• Performance and Power Configurable output drive strength
• Power Saving Modes
• Hybrid Sleep Mode
• Deep Power Down
• Configurable Burst Characteristics
• Linear burst
• Wrapped burst lengths: 16 bytes (8 clocks), 32 bytes (16 clocks), 64 bytes (32 clocks), 128 bytes (64 clocks)
• Hybrid burst - one wrapped burst followed by linear burst
• Array Refresh Modes
• Full Array Refresh
• Partial Array Refresh
• Support package: 24 balls TFBGA
• Operating temperature range: -40℃ ≤ TCAS ≤ 85℃