SN74AUP1T50DCKR

The SN74AUP1T50 performs the Boolean function Y = A, specified for logic level translation applications where the output is referenced to the supply VCC. AUP technology is a low-power logic technology designed to extend battery life in operating applications. All inputs accept 1.8V LVCMOS signal levels while operating from a single 3.3V or 2.5V VCC supply. The wide VCC range of 2.3V to 3.6V enables switching output levels to interface with external controllers or processors. Schmitt-trigger inputs (ΔVT = 210mV between positive and negative-going thresholds) improve noise immunity during switching transitions, which is beneficial for mixed analog-mode designs. Schmitt-trigger inputs suppress input noise, ensure output signal integrity, and accommodate slow input signal transitions. The power-off feature enables a power-saving condition (VCC = 0V); when VCC = 0V, signals in the range of 0V to 3.6V can be applied to the inputs and outputs of the device. Under these conditions, no damage to the device will occur. The SN74AUP1T50 is designed with an optimized 4mA current drive capability to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

Key features

• Single-supply voltage translator with output levels up to supply VCC CMOS levels
• 1.8V to 3.3V (VCC = 3.3V)
• 2.5V to 3.3V (VCC = 3.3V)
• 1.8V to 2.5V (VCC = 2.5V)
• 3.3V to 2.5V (VCC = 2.5V)
• Schmitt-trigger inputs suppress input noise and provide improved output signal integrity
• I off supports partial power-down (VCC = 0)
• Ultra-low quiescent power consumption: 0.1μ
• Ultra-low dynamic power consumption: 0.9μ
• Latch-up performance exceeds 100mA (per JESD 78, Class II)
• Available in lead-free package: SC-70 (DCK)
• ESD performance tested per JESD 22 – 2000V Human Body Model (A114-B, Class II), 1000V Charged Device Model (C101)