74AUP1G07GW,125

The 74AUP1G07 is a single buffer with open-drain output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The l(OFF) circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Applications

• Low-power buffer
• Open-drain output
• Partial power-down applications

Key features

• Wide supply voltage range from 0.8 V to 3.6 V
• High noise immunity
• CMOS low power dissipation
• Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V)
• Low static power consumption; l(CC) = 0.9 μA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Overvoltage tolerant inputs to 3.6 V
• Low noise overshoot and undershoot < 10 % of V(CC)
• IOFF circuitry provides partial Power-down mode operation
• Multiple package options
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C