EM74LVC1G07GW

The EM74LVC1G07 is a single buffer with an open-drain output. Its input can be driven by 3.3 V or 5 V devices. This feature allows the device to be used as a level translator in mixed 3.3 V and 5 V environments. Schmitt-trigger action on all inputs enables the circuit to tolerate slower input rise and fall times. The device is fully specified for partial-power-down applications using the IOFF circuit. The IOFF circuit disables the outputs, preventing potentially damaging reverse current from flowing through the device when it is powered down.

Key features

• Wide supply voltage range: 1.65 V ~ 5.5 V
• Input overvoltage tolerance up to 5.5 V
• High noise immunity
• CMOS low power consumption
• IOFF circuitry supports partial power-down mode operation
• ±24 mA output drive capability (VCC = 3.0 V)
• Latch-up performance exceeds 100 mA
• Direct TTL-level interface compatible
• Compliant with JEDEC standards: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD36 (4.5 V to 5.5 V)
• ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V, MM JESD22-A115C Class C exceeds 550 V, CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
• Multiple package options